1. Technical Field
The present invention is in the field of semiconductor processing and devices, more specifically in the field of non-volatile charge-trapping memory devices. In particular, the present invention relates to a method for extracting the spatial distribution of charge stored in a charge-trapping layer of a semiconductor device, according to the preamble of the first claim.
2. Background Art
Non-volatile memories (NVM) are characterized by the fact that once a bit is stored in a memory cell this bit will be retained even when the memory cell is no longer powered. When electrical fields are used for erasing and programming of the memory cell, the NVM devices are also known as EEPROM (Electrically-Erasable-and-Programmable-Read-Only-Memory) devices. Whereas in floating gate EEPROM devices charge is stored in a conductive layer being part of a double-capacitor structure, in charge-trapping EEPROM devices charge is stored in a non-conductive layer being part of a single-capacitor structure. In such non-conductive charge-storage layer, e.g. nitride, oxide containing polysilicon nanocrystals or metal nanoparticles, the charge will not spread out uniformly over the whole of the charge-storage layer but will be confined substantially to the location where the charge was introduced into this non-conductive charge-storage layer. Charge-trapping memory devices are characterized by the presence of discrete charge traps as memory elements contrary to floating gate memory devices where a conductive layer is used as one continuous charge trap for storing charge. Developments in EEPROM devices are increasingly focused on localized charge trapping because it eases integration and reduces stress-induced-leakage. In particular NROM™ devices using nitride as non-conductive charge-storage layer as disclosed for example by B. Eitan in international application W099/070000, are very attractive since they allow storage of two physical bits per memory cell, each bit at a different location in the nitride charge-storage layer. By injecting carriers, e.g. electrons, in the nitride layer the NROM™ cell is programmed. In order to erase the NROM™ cell opposite-type carriers are injected in the nitride layer as to compensate the charge stored during programming, e.g. holes are injected in the nitride layer to compensate the electrons already present. However, poor endurance and poor retention after cycling, i.e. repetitive programming and erasing of a cell, are major drawbacks of NROM™.
Currently the exact cause of the poor endurance and poor charge retention properties of non-volatile charge-trapping memory devices, in particular of NROM™ devices, is not yet known, impeding the improvement of these properties. One method to determine the lateral distribution of charge in MOSFET-type devices is the technique known as Charge-Pumping (CP). This method was initially developed to study hot-carrier-induced degradation mechanisms in MOSFET-type devices. Charge-pumping measurements are a powerful technique for obtaining information on the charge trapped in a MOSFET-type device by scanning the threshold voltage along the channel of the device. M. Rosmeulen et al teaches in “Characterization of the spatial charge distribution in local charge-trapping memory devices using the charge-pumping technique”, (Solid-State Electronics journal, volume 48 (2004) p 1525-1530), the application of the charge-pumping technique to non-volatile memory devices which are based on localized trapping of charge, in particular to n-type NROM™ devices using nitride or silicon-rich-oxide as trapping medium and injection of electrons for programming the memory cell. In particular section 3.3 of this disclosure, hereby incorporated by reference in its entirety, teaches how the lateral distribution of the total charge trapped in the device can be directly calculated from the charge-pumping measurements using a deconvolution-based procedure. Although this measurement procedure allows extracting the lateral distribution of electrons injected in the device during a programming step, it doesn't take into account the variation of the density of charge traps present at the interface between the channel and the dielectric stack and assumes this density to be uniform along the channel. Moreover when the device is subjected to multiple program/erase steps, this interface will be degraded due to this electrical stress. Additional interface traps Nit will be formed in a non-uniform way, in particular when erasing the memory device by injection of holes. Due to the sensitivity of the charge-pumping measurements to this interface degradation, an accurate extraction of the lateral distribution of charge injected in the trapping medium during a programming or erasing step in a degraded device is therefore impossible due the non-uniform distribution of the interface traps.
On the other hand Chim et al. describe in “Extraction of metal-oxide-semiconductor field-effect-transistor interface state and trapped charge spatial distributions using a physics-based algoritm” (Journal Applied Physics, volume 81(4) (1997), p 1993-2001) a charge extraction algorithm based on charge-pumping measurement data to gain insight in the hot-carrier-induced degradation mechanisms of MOSFETs and to extract both interface traps Nit and oxide charge Not. However as this technique is based on an iteration scheme starting from values of interface traps, local threshold voltages etc, which are estimated in view of the expected results, its accuracy can be questioned.
Thus, there is a need for a method to determine the spatial distribution of charge trapped in a dielectric and in interface traps of a MOSFET-type device.